Method and system for isolated and discretized process sequence integration
US8486844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2012 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Aug 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67769
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.