Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US8487348B2 · kind B2 · utility
7Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2012 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Aug 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/791
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.