Patent · US Active

Low impedance gate control method and apparatus

US8487407B2 · kind B2 · utility

11Cited by

2References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Reinhold Bayerer · Warstein, DE
Daniel Domes · Schwäbisch Hall, DE

Key dates

Filing date	Oct 13, 2011
Grant date	Jul 16, 2013
Priority date	—
Expiry date	Jan 16, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3011
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.