Graded metal oxide resistance based semiconductor memory device
US8488362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jul 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.