Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate
US8488388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Feb 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.