Efficient data prefetching in the presence of load hits
US8489823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2012 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jun 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.