Executing a perform frame management instruction
US8489853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2012 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Mar 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.