Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process
US8492208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2012 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jan 5, 2032 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.