FinFET with stressors
US8492235B2 · kind B2 · utility
22Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Apr 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
Abstract
A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.