Methods of forming a masking pattern for integrated circuits
US8492282B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2009 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Feb 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.