On-chip cooling for integrated circuits
US8492295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.