Through silicon via direct FET signal gating

US8492903B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gerald K. Bartley · Rochester, US
• Philip Raymond Germann · Oronoco, US
• David P. Paulsen · Dodge Center, US
• John E. Sheets, II · Zumbrota, US

Key dates

• Filing date: Jun 29, 2011
• Grant date: Jul 23, 2013
• Expiry date: Oct 18, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06544
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV.