Underfill method and chip package
US8492910B2 · kind B2 · utility
0Cited by
6References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2012 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.