Reliability support in memory systems without error correcting code support
US8495464B2 · kind B2 · utility
1Cited by
13References
14Claims
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Key dates
| Filing date | Jun 28, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6566
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.