Stress reduction in chip packaging by a stress compensation region formed around the chip

US8497583B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Dmytro Chumakov · Dresden, DE
• Michael Grillberger · Radebeul, DE
• Heike Berthold · Zeitz, DE
• Katrin Reiche · Goltzscha, DE

Key dates

• Filing date: Dec 9, 2010
• Grant date: Jul 30, 2013
• Expiry date: Nov 4, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.