Two-transistor floating-body dynamic memory cell
US8498140B2 · kind B2 · utility
13Cited by
7References
35Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 1, 2008 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Sep 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.