Etch stop layers and methods of forming the same
US8502286B2 · kind B2 · utility
3Cited by
0References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 22, 2010 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Aug 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8311
Abstract
A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.