Patent · US Active

SRAM memory cell provided with transistors having a vertical multichannel structure

US8502318B2 · kind B2 · utility

12Cited by

12References

14Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Olivier Thomas · Saint-Martin-d'Hères, FR
Thomas Ernst · Morette, FR

Key dates

Filing date	Nov 7, 2008
Grant date	Aug 6, 2013
Priority date	—
Expiry date	May 2, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k≧1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.