Memory controller, system and method for read signal timing calibration
US8504788B2 · kind B2 · utility
24Cited by
2References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Jun 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.