Patent · US Active

Method for partitioning scan chain

US8504886B2 · kind B2 · utility

0Cited by
8References
5Claims
0Family size

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Key dates

Filing dateJul 27, 2011
Grant dateAug 6, 2013
Priority date—
Expiry dateDec 4, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318536
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A system and method for scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device is provided. One or more scan partitions in the embedded logic circuit are identified. Each scan partition includes one or more scan chains of scan registers. One or more interacting registers connecting scan registers of a first scan partition and scan registers of a second scan partition are identified and combined to form an interacting scan chain. The embedded logic circuit is tested by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.