Method and apparatus for performing automated timing closure analysis for systems implemented on target devices
US8504970B1 · kind B1 · utility
8Cited by
0References
26Claims
0Family size
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Key dates
| Filing date | Jul 5, 2011 |
| Grant date | Aug 6, 2013 |
| Priority date | — |
| Expiry date | Jul 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a design for a system to be implemented on a target device includes compiling the design. Information used to make a compilation decision on the design is stored. A strategy to improve timing closure on a signal path on the design is derived using the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.