Patent · US Active

Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof

US8508984B2 · kind B2 · utility

31Cited by

60References

25Claims

0Family size

Assignee

Avalanche Technology, Inc. · US

Inventors

Rajiv Yadav Ranjan · San Jose, US
Parviz Keshtbod · Los Altos Hills, US
Roger Klas Malmhall · San Jose, US

Key dates

Filing date	Feb 29, 2008
Grant date	Aug 13, 2013
Priority date	—
Expiry date	Nov 27, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH10N50/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.