Memory device and related operating methods
US8509017B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2011 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Nov 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.