Method for evaluating failure rate
US8510635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2010 |
| Grant date | Aug 13, 2013 |
| Priority date | — |
| Expiry date | Dec 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.