Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8513813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2012 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.