Detection of word-line leakage in memory arrays: current based approach
US8514630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2011 |
| Grant date | Aug 20, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.