Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure
US8518792B2 · kind B2 · utility
5Cited by
22References
33Claims
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Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Aug 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.