Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof
US8520391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2011 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Feb 24, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.