Arithmetic decoding acceleration
US8520740B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 2, 2010 |
| Grant date | Aug 27, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/91
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for performing decoding of context-adaptive binary arithmetic coding (CABAC) encoded data. The mechanisms receive, in a first single instruction multiple data (SIMD) vector register of the data processing system, CABAC encoded data of a bit stream. The CABAC encoded data includes a value to be decoded and bit stream state information. The mechanisms receive, in a second SIMD vector register of the data processing system, CABAC decoder context information. The mechanisms process the value, the bit stream state information, and the CABAC decoder context information in a non-recursive manner to generate a decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms store, in a third SIMD vector register, a result vector that combines the decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms use the decoded value to generate a video output on the data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.