Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
US8524562B2 · kind B2 · utility
8Cited by
2References
20Claims
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Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Apr 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.