Methods for the fabrication of integrated circuits including back-etching of raised conductive structures

US8524566B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stefan Flachowsky · Dresden, DE
• Ricardo P. Mikalo · Stadtroda, DE
• Jan Hoentschel · Dresden, DE

Key dates

• Filing date: Dec 20, 2011
• Grant date: Sep 3, 2013
• Expiry date: Mar 4, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.