eDRAM having dynamic retention and performance tradeoff
US8525245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2011 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Jan 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.