Memory device data latency circuits and methods
US8527802B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2012 |
| Grant date | Sep 3, 2013 |
| Priority date | — |
| Expiry date | Dec 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.