ETSOI CMOS with back gates
US8530287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Sep 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.