Method of fabricating a dummy gate structure in a gate last process
US8530326B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jun 29, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jun 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.