Planar encapsulation and mold cavity package in package system
US8531043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2008 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Nov 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system includes: providing a substrate; mounting a first package above the substrate, the first package having a mold cavity exposing an exposed portion on a first integrated circuit from a first package encapsulation; mounting a second package above the first package and attached to the exposed portion of the first integrated circuit; mounting a structure above the second package and connected to the substrate around the first package; and encapsulating the first package and the second package with an outer encapsulation having a completely planar top or a planar top co-planar to a top surface of the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.