Guaranteed prefetch instruction
US8533437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Apr 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a cache memory, an instruction set having first and second prefetch instructions each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory, and a memory subsystem configured to execute the first and second prefetch instructions. For the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a predetermined set of conditions. For the second prefetch instruction the memory subsystem is configured to complete prefetching the cache line of data from the system memory into the cache memory in response to the predetermined set of conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.