System and method of error correction of control data at a memory device
US8533558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2010 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jul 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/403
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.