Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design
US8533647B1 · kind B1 · utility
7Cited by
17References
12Claims
0Family size
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Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to realize some of the advantages described above, there is provided a computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC). The method comprises generating a plurality of verification specific abstracted views of the IP core each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.