Providing conversion of a planar design to a FinFET design
US8533651B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2012 |
| Grant date | Sep 10, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.