Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8535989B2 · kind B2 · utility
33Cited by
64References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2010 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Jun 1, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.