Configuration of a multi-die integrated circuit
US8536895B2 · kind B2 · utility
2Cited by
14References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Sep 17, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.