Method of manufacturing dummy gates in gate last process
US8541296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2011 |
| Grant date | Sep 24, 2013 |
| Priority date | — |
| Expiry date | Nov 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.