Patent · US Active

Prefetching with multiple processors and threads via a coherency bus

US8543767B2 · kind B2 · utility

3Cited by

17References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Gordon B. Bell · Madison, US
Gordon Taylor Davis · Boca Raton, US
Jeffrey H. Derby · Chapel Hill, US
Anil Krishna · Cary, US
Srinivasan Ramani · Cary, US
Ken V. Vu · Cary, US
Steve Woolet · Raleigh, US

Key dates

Filing date	Jun 4, 2012
Grant date	Sep 24, 2013
Priority date	—
Expiry date	Jun 4, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/6026
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.