Replacement metal gate processing with reduced interlevel dielectric layer etch rate

US8546209B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Junli Wang · Slingerlands, US
• Keith Kwong Hon Wong · Wappingers Falls, US
• Chih-Chao Yang · Glenmont, US

Key dates

• Filing date: Jun 15, 2012
• Grant date: Oct 1, 2013
• Expiry date: Jun 15, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A method of forming a semiconductor device structure includes forming an interlevel dielectric (ILD) layer over a semiconductor substrate and a dummy transistor gate structure formed on the substrate; infusing a shallow gas cluster ion beam (GCIB) layer in a top portion of the ILD layer; and removing at least one layer from the dummy transistor gate structure, wherein the at least one layer comprises a same material as the ILD layer and wherein the GCIB layer has a slower etch rate with respect to the ILD layer.