Memory arrays and methods of forming memory cells

US8546231B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Fabio Pellizzer · Boise, US
• Roberto Bez · Milano, IT
• Lorenzo Fratin · Buccinasco Castello, IT

Key dates

• Filing date: Nov 17, 2011
• Grant date: Oct 1, 2013
• Expiry date: Feb 4, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8828

Abstract

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.