Methods of fabricating non-volatile memory with air gaps
US8546239B2 · kind B2 · utility
25Cited by
10References
38Claims
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Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.