Hybrid multilayer substrate
US8546921B2 · kind B2 · utility
2Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2010 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Nov 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A hybrid multilayer substrate in an electronic package. The substrate includes a first portion having m layers and a second portion having n layers such that m is less than n. The first portion has a first height and the second portion has a second height. The first height is different than the second height. In another embodiment, a surface is formed between the first portion and the second portion, and a shielding material can be applied to the surface. In a different embodiment, the hybrid multilayer substrate is manufactured for shielding a first die from a second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.