Methods and devices for memory reads with precharged data lines
US8547750B2 · kind B2 · utility
8Cited by
11References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 7, 2011 |
| Grant date | Oct 1, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage. Various embodiments include the array architecture to facilitate precharging the adjacent pair of data lines to a particular voltage and maintaining the unselected data line at the particular voltage during a sensing phase of a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.