Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps
US8552515B2 · kind B2 · utility
5Cited by
24References
71Claims
0Family size
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Key dates
| Filing date | Aug 8, 2012 |
| Grant date | Oct 8, 2013 |
| Priority date | — |
| Expiry date | Aug 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
Abstract
Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.